Non-volatile memory cells, in which each cell has at least four terminals, formed in an array are well known in the art. Referring to FIG. 1 there is shown a block level diagram of a memory cell array 10 of the prior art. The array 10 is composed of cells 20 arranged in a plurality of rows and columns. Each cell 20 has a structure whose cross-sectional view is shown in FIG. 2.
The cell 20 comprises a semiconductor substrate 12 of one conductivity type, such as P type. A first region 22 of a second conductivity type is in the substrate 12. A second region 24 of the second conductivity type is also in the substrate 12. The first region 22 and the second region 24 are separated by a channel region 26. A floating gate 28 is spaced apart from the substrate 12 and is insulated from a portion of the channel region 26. A control gate 30 is spaced apart from the substrate 12 and is insulated from another portion of the channel region 26. Finally, a coupling gate 32 is positioned above the floating gate 28 and is capacitively coupled to the floating gate 28.
The connection of the cells 20 in the array 10 is as follows. The cells 20 are arranged in a plurality of rows and columns. As will be appreciated by those skilled in the art, the term “row” and “column” may be used interchangeably. For cells 20 in the same column, a bit line or BL connects the first region 22 of all the cells 20 in the same column. For cells in the same row a word line or WL connects the control gate 30 of all the cells 20 in the same row. In addition, the coupling gate 32 or CG of all the cells 20 in the same row are connected together. Finally, for the cells 20 in the same row, the common source 24 or the second region 24 are connected together.
In the prior art, it is also well known that to address a particular Bit Line, a column decoder 40 receives an address signal and decodes the signal and selects the particular Bit Line. Further, a row decoder 50 receives another address signal and decodes the signal and selects the particular Word Line. The intersection of the particular Bit Line and the particular Word Line selects a unique cell 20 within the array 10, for a particular operation, which can be operations such as erase, program, or read. When a particular Bit Line or a particular Word Line is selected, it is meant that certain voltages are applied to those lines. However, because the cell 20 is a multi-terminal cell 20, i.e. it comprises a plurality (>3) terminals, voltages may also need to be provided to the other terminals of the cell 20. Since the particular cell 20 has been determined by the selection of one particular Bit Line and one particular Word Line, the other lines to the determined cell, such as CS and CG, need not be selected based upon only one single CS line or only one single CG line. Thus, the decoding of the address signal to select, e.g. the CG line, need not be based upon the decoding of the complete address signal, so long as the selected CG line is one of a plurality of CG lines selected. Thus, as shown schematically in FIG. 1, the CG line is decoded based upon decoding circuit within the row decoder 50, which does not completely decode the address signal. Therefore, a plurality of CG lines, including the CG line connected to the selected cell 20, are all activated at the same time. Similarly, the selected CS line need not be based upon the complete decoding of the address signal, and may be based upon a partial address signal, so long as the selected CS line is one of a plurality of CS lines selected. The benefit of such a scheme is clear. The row decoder 50 (and the common source decoder 60) to decode the address signal for the CG and CS lines do not have to be complete decoders, thereby saving circuitry, resulting in less area needed for these peripheral (outside of the main cell array 10) circuits.
Referring to FIG. 3, there is shown a schematic circuit diagram of a portion of the array 10 with the voltages showing the programming of the array 10 of a particular cell 20. As shown in FIG. 3, the particular cell 20 to be programmed (labeled as “Selected pgm cell 20” shown in FIG. 3) is applied with the following voltages: BL=0.4 volts; WL=2.0 volts. All the non-selected BL have a voltage of Vcc-Vth. All the non-selected WL have a voltage of 0.0 volts. The CG line to the Selected pgm cell 20, along with 7 other CG lines to the non-selected cells are supplied with the voltage of 10.5 volts. The CS line to the Selected pgm cell 20, along with 7 other CS lines to the non-selected cells are supplied with the voltage of 4.5 volts.
Selected cell: BL=0.4 v; WL=2.0v; CG=10.5 v; CS=4.5 v
Non-selected cell in a different row, such as cell labeled as “Disturbed Cell A” (hereinafter referred to simply as “cell A”) shown in FIG. 3: BL=Vcc-Vth v; WL=0.0v; CG=10.5 v; CS=4.5 v
Non-selected cell in the same row, such as cell labeled as “Disturbed Cell B” (hereinafter referred to simply as “cell B”) shown in FIG. 3: BL=Vcc-Vth v; WL=2.0v; CG=10.5 v; CS=4.5 v
During programming electrons are injected onto the floating gate 28 from the channel region 26. However, with the foregoing voltages, during programming operation, and because of the structure of the cell 20, the program disturbance (for reverse program tunneling from the WL to the Floating Gate) to Cell A is worst than the program disturbance to Cell B.
Accordingly there is a need to minimize program disturbance, or other operational disturbance on the memory array 10 without unduly increase the decoding circuit required.
Finally, interleaving of strap lines to prevent punch through is also well known in the art. See U.S. Pat. No. 6,822,287.